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MT8888C Integrated DTMF Transceiver with Intel Micro Interface
Data Sheet Features
* * * * * * Central office quality DTMF transmitter/receiver Low power consumption High speed Intel micro interface Adjustable guard time Automatic tone burst mode Call progress tone detection to -30dBm Ordering Information MT8888CE MT8888CS MT8888CN MT8888CP 20 20 24 28 Pin Plastic DIP Pin SOIC Pin SSOP Pin Plastic LCC
February 2004
Applications
* * * * * Credit card systems Paging systems Repeater systems/mobile radio Interconnect dialers Personal computers
-40C to +85C The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8888C utilizes an Intel micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic.
Description
The MT8888C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.
TONE
D/A Converters
Row and Column Counters
Transmit Data Register Status Register
Data Bus Buffer
D0 D1 D2 D3
Tone Burst Gating Cct. IN+ INGS OSC1 OSC2 Oscillator Circuit Bias Circuit VDD VRef VSS + Dial Tone Filter
Control Logic
Interrupt Logic IRQ/CP
High Group Filter Low Group Filter Control Logic
Digital Algorithm and Code Converter
Control Register A Control Register B I/O Control
RD CS WR RS0
Steering Logic
Receive Data Register
ESt
St/GT
Figure 1 - Functional Block Diagram 1
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MT8888C
Data Sheet
GS NC ININ+ VDD St/GT EST
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections Pin Description Pin # 20 1 2 3 4 5 6 7 24 1 2 3 4 5 6 7 28 1 2 4 6 7 8 9 Name IN+ INGS VRef VSS Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Description
OSC1 DTMF clock/oscillator input. Connect a 4.7M resistor to VSS if crystal oscillator is used. OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. TONE Output from internal DTMF transmitter. WR CS RS0 RD Write microprocessor input. TTL compatible. Chip Select input. Active Low. This signal must be qualified externally by address latch enable (ALE) signal, see Figure 14. Register Select input. Refer to Table 3 for bit interpretation. TTL compatible. Read microprocessor input. TTL compatible.
8 9 10 11 12 13
10 11 12 13 14 15
12 13 14 15 17 18
IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1. TTL compatible.
14-17 18-21 19-22
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TONE WR CS RSO NC RD IRQ/CP
IN+ INGS VRef VSS OSC1 OSC2 TONE WR CS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD St/GT ESt D3 D2 D1 D0 IRQ/CP RD RS0
IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE WR CS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP RD RS0
12 13 14 15 16 17 18
NC VRef VSS OSC1 OSC2 NC NC
4 3 2 1 28 27 26
5 6 7 8 9 10 11
*
25 24 23 22 21 20 19
NC NC NC D3 D2 D1 D0
28 PIN PLCC
MT8888C
Pin Description (continued) Pin # 20 18 24 22 28 26 Name ESt Description
Data Sheet
Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (5V typical). No Connection.
19
23
27
St/GT
20
24
28
VDD NC
8, 9, 3,5,10, 16,17 11,16, 23,25
1.0
Functional Description
The MT8888C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The Intel micro interface allows microcontrollers, such as the 8080, 80C31/51 and 8085, to access the MT8888C internal registers.
2.0
Input Configuration
The input arrangement of the MT8888C provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the opamp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration.
3.0
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). These filters incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.
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MT8888C
Data Sheet
IN+
C
RIN
IN-
RF
GS
VRef VOLTAGE GAIN (AV) = RF / RIN MT8888C
Figure 3 - Single-Ended Input Configuration
C1
R1
IN+
INC2 R4 R5 GS R3 R2 VRef MT8888C DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 k R2 = 60k, R3 = 37.5 k R3 = (R2R5)/(R2 + R5) VOLTAGE GAIN (AV diff) - R5/R1 INPUT IMPEDANCE (ZINdiff) = 2 R12 + (1/C)2
Figure 4 - Differential Input Configuration
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FLOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941
Note: 0= LOGIC LOW, 1= LOGIC HIGH
Data Sheet
FHIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
DIGIT 1 2 3 4 5 6 7 8 9 0 * # A B C D
D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 1 - Functional Encode/Decode Table Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.
4.0
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
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MT8888C
Data Sheet
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
VDD MT8888C VDD St/GT ESt R1 C1 Vc
tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
5.0
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): tREC tDPmax+tGTPmax - tDAmin tREC tDPmin+tGTPmin - tDAmax tID tDAmax+tGTAmax - tDPmin tDO tDAmin+tGTAmin - tDPmax
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MT8888C
tGTP = (RPC1) In [VDD / (VDD-VTSt)] tGTA = (R1C1) In (VDD/VTSt) VDD C1 St/GT RP = (R1R2) / (R1 + R2)
Data Sheet
R1 ESt
R2 a) decreasing tGTP; (tGTP < tGTA)
tGTP = (R1C1) In [VDD / (VDD-VTSt)] VDD C1 St/GT tGTA = (RpC1) In (VDD/VTSt) RP = (R1R2) / (R1 + R2)
R1 ESt
R2 b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 F is recommended for most applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP) and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.
6.0
Call Progress Filter
A call progress mode, using the MT8888C, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the `accept' bandwidth limits of the filter, are hard-limited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the `reject' area will not be detected and consequently the IRQ/CP pin will remain low.
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MT8888C
EVENTS tREC Vin tDP ESt tGTP A tREC TONE #n tDA tGTA B tID TONE #n + 1 C D tDO TONE #n + 1 E
Data Sheet
F
St/GT tPStRX RX0-RX3 DECODED TONE # (n-1) #n tPStb3 b3 # (n + 1)
VTSt
b2
Read Status Register IRQ/CP
Figure 7 - Receiver Timing Diagram
LEVEL (dBm)
-25
0 = Reject
250
500
750
FREQUENCY (Hz)
= May Accept = Accept
Figure 8 - Call Progress Response
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EXPLANATION OF EVENTS A) B) C) D) E) F)
Data Sheet
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS Vin ESt St/GT RX 0-RX 3 b3 DTMF COMPOSITE INPUT SIGNAL. EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. 4-BIT DECODED DATA IN RECEIVE DATA REGISTER DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL. INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ. INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED AFTER THE STATUS REGISTER IS READ. MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TIME TO DETECT VALID FREQUENCIES PRESENT. TIME TO DETECT VALID FREQUENCIES ABSENT. GUARD TIME, TONE PRESENT. GUARD TIME, TONE ABSENT.
b2 IRQ/CP t REC t REC t ID t DO tDP tDA tGTP tGTA
Figure 9 - Description of Timing Events
7.0
DTMF Generator
The DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to com-pensate for high group attenuation on long loops.
The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.
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MT8888C
Data Sheet
The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no "start-up" time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 8 that the distortion products are very low in amplitude.
Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz
Figure 10 - Spectrum Plot
8.0
Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms1 ms, which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration is doubled to 102 ms 2 ms. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter.
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MT8888C
9.0 Single Tone Generation
Data Sheet
A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details. ACTIVE INPUT L1 L2 L3 L4 H1 H2 H3 H4 OUTPUT FREQUENCY (Hz) %ERROR SPECIFIED 697 770 852 941 1209 1336 1477 1633 ACTUAL 699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 1645.0 +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73
Table 2 - Actual Frequencies Versus Standard Requirements
10.0
Distortion Calculations
The MT8888C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage.
V22f + V23f + V24f + .... V2nf THD (%) = 100 Vfundamental
Figure 11 - Equation 1. THD (%) For a Single Tone The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2. VL and VH correspond to the low group amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10.
V22L + V23L + .... V2nL + V22H + V23H + .. V2nH + V2IMD THD (%) = 100 V2L + V2H
Figure 12 - Equation 2. THD (%) For a Dual Tone
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11.0 DTMF Clock Circuit
Data Sheet
The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal specification is as follows:
Frequency: Frequency Tolerance: Resonance Mode: Load Capacitance:
3.579545 MHz 0.1% Parallel 18pF
Maximum Series Resistance: 150 ohms Maximum Drive Level: 2mW
e.g.
CTS Knights MP036S Toyocom TQC-203-A-9S
A number of MT8888C devices can be connected as shown in Figure 13 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected.
MT8888C OSC1 OSC2
MT8888C OSC1 OSC2
MT8888C OSC1 OSC2
3.579545 MHz
Figure 13 - Common Crystal Connection
12.0
Microprocessor Interface
The MT8888C incorporates an Intel microprocessor interface which is compatible with fast versions (16 MHz) of the 80C51. No wait cycles need to be inserted. Figure 19 and Figure 20 are the timing diagrams for the Intel 8031, 8051 and 8085 (5 MHz) microcontrollers. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS is generated. Figure 14 summarizes the connection of these Intel processors to the MT8888C transceiver. The microprocessor interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Table 6 and Table 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8). A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 19). Refer to Tables 4-7 for bit descriptions of the two control registers.
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MT8888C
Data Sheet
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a squarewave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 15). RS0 0 0 1 1 WR 0 1 0 RD 1 0 1 FUNCTION Write to Transmit Data Register Read from Receive Data Register Write to Control Register
1 0 Read from Status Register Table 3 - nternal Register Functions b3
RSEL
b2
IRQ
b1
CP/DTMF
b0
TOUT
Table 4 - CRA Bit Positions
b3 C/R b2 S/D b1 TEST b0 BURST ENABLE
Table 5 - CRB Bit Positions BIT b0 b1 NAME TOUT CP/DTMF DESCRIPTION Tone Output Control. A logic high enables the tone output; a logic low turns the tone output off. This bit controls all transmit tone functions. Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode; a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and transmitting DTMF signals. In CP mode a rectangular wave representation of the received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control register A, b2=1). In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the interrupt function. When IRQ is enabled and DTMF mode is selected (control register A, b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). Register Select. A logic high selects control register B for the next write cycle to the control register address. After writing to control register B, the following control register write cycle will be directed to control register A. Table 6 - Control Register A Description
b2
IRQ
b3
RSEL
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MT8888C
BIT b0 NAME BURST DESCRIPTION
Data Sheet
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been enabled. When CP mode (control register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (control register A, b0). Test Mode Control. A logic high enables the test mode; a logic low de-activates the test mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the signal present on the IRQ/CP pin will be analogous to the state of the DELAYED STEERING bit of the status register (see Figure 7, signal b3). Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires further selection of either the row or column tones (low or high group) through the C/R bit (control register B, b3). Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone output. This function is used in conjunction with the S/D bit (control register B, b2). Table 7 - Control Register B Description
b1
TEST
b2
S/D
b3
C/R
BIT b0 b1
NAME IRQ TRANSMIT DATA REGISTER EMPTY (BURST MODE ONLY) RECEIVE DATA REGISTER FULL DELAYED STEERING
STATUS FLAG SET Interrupt has occurred. Bit one (b1) or bit two (b2) is set. Pause duration has terminated and transmitter is ready for new data. Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 8 - Status Register Description
STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. Cleared after Status Register is read. Cleared upon the detection of a valid DTMF signal.
b2 b3
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MT8888C
Data Sheet
8031/8051 8080/8085 A8-A15 A8
MT8888C CS RS0 D0-D3
PO RD WR
RD WR
Figure 14 - MT8888C Interface Connections for Various Intel Micros
VDD MT8880C C1 DTMF/CP INPUT R2 R1 IN+ INGS VRef VSS OSC1 R5 X-tal DTMF OUTPUT C4 RL OSC2 TONE WR CS Notes: R1, R2 = 100 k 1% R3 = 374 k 1% R4 = 3.3 k 10% R5 = 4.7 M 10% RL = 10 k (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* C4 = 10 nF 10% X-tal = 3.579545 MHz VDD St/GT ESt D3 D2 D1 D0 IRQ/CP RD RS0 To P or C R3 C2 R4
C3
* Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8888C can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided.
Figure 15 - Application Circuit (Single-Ended Input)
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Data Sheet
5.0 VDC MMD6150 (or equivalent) 2.4 k
5.0 VDC 3 k
TEST POINT
TEST POINT
130 pF
24 k MMD7000 (or equivalent)
100 pF
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 16 - Test Circuits
INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up.The initialization procedure should be implemented 100ms after power up. Description: 1) 2) 3) 4) 5) 6) Read Status Register Write to Control Register Write to Control Register Write to Control Register Write to Control Register Read Status Register RS0 1 1 1 1 1 1 Control WR 1 0 0 0 0 1 RD 0 1 1 1 1 0 b3 X 0 0 1 0 X Data b2 X 0 0 0 0 X b1 X 0 0 0 0 X b0 X 0 0 0 0 X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 WR RD b3 1) Write to Control Register A 1 0 1 1 (tone out, DTMF, IRQ, Select Control Register B) 2) Write to Control Register B 1 0 1 0 (burst mode) 3) Write to Transmit Data Register 0 0 1 0 (send a digit 7) 4) Wait for an interrupt or poll Status Register 5) Read the Status Register 1 1 0 X -if bit 1 is set, the Tx is ready for the next tone, in which case... Write to Transmit Register 0 0 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case.... Read the Receive Data Register 0 1 1 0
b2 1 0 1
b1 0 0 1
b0 1 0 1
X 1
X 0
X 1
0
X
X
X
X
-if both bits are set... Read the Receive Data Register 0 1 0 X X X X Write to Transmit Data Register 0 0 1 0 1 0 1 NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms ( 4 ms).
Figure 17 - Application Notes
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Zarlink Semiconductor Inc.
MT8888C
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Power supply voltage VDD-VSS Voltage on any pin Current at any pin (Except VDD and VSS) Storage temperature Package power dissipation TST PD -65 Symbol VDD VI VSS-0.3 Min Max 6
Data Sheet
Units V V mA C mW
VDD+0.3 10 +150 1000
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 Positive power supply Operating temperature
Sym VDD TO
Min 4.75 -40
Typ 5.00
Max 5.25 +85
Units V C
Test Conditions
Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz Typical figures are at 25 C and for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics
-V SS=0 V.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D i g i t a l Data Bus O U T P U T S S U P I N P U T S
Sym VDD IDD PC VIHO VILO VTSt VOLO VOHO IOZ VRef ROR VIL VIH IIZ
Min 4.75
Typ 5.0 7.0
Max 5.25 11 57.8
Units V mA mW V
Test Conditions
Operating supply voltage Operating supply current Power consumption High level input voltage (OSC1) Low level input voltage (OSC1) Steering threshold voltage Low level output voltage (OSC2) High level output voltage (OSC2) Output leakage current (IRQ) VRef output voltage VRef output resistance Low level input voltage High level input voltage Input leakage current
3.5 1.5 2.2 2.3 2.5 0.1 4.9 1 2.4 2.5 1.3 0.8 2.0 10 10 2.6
Note 9* Note 9* VDD=5V No load Note 9* No load Note 9* VOH=2.4 V No load, VDD=5V
V V V V A V k V V A
VIN=VSS to VDD
15 16
Source current Sink current
IOH IOL
-1.4 2.0
-6.6 4.0
mA mA
VOH=2.4V VOL=0.4V
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Zarlink Semiconductor Inc.
MT8888C
DC Electrical Characteristics (continued)
- VSS=0 V. (continued)
Data Sheet
Characteristics 17 18 19
ESt and St/Gt IRQ/ CP
Sym IOH IOL IOL
Min -0.5 2 4
Typ -3.0 4 16
Max
Units mA mA mA
Test Conditions VOH=4.6V VOL=0.4V VOL=0.4V
Source current Sink current Sink current
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25 C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See "Notes" following AC Electrical Characteristics Tables.
Electrical Characteristics Gain Setting Amplifier
- Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection DC open loop voltage gain Unity gain bandwidth Output voltage swing Allowable capacitive load (GS) Allowable resistive load (GS) Common mode range
Sym IIN RIN VOS PSRR CMRR AVOL BW VO CL RL VCM
Min
Typ
Max 100
Units nA M
Test Conditions VSS VIN VDD
10 25 50 40 40 1.0 0.5 VDD-0.5 100 50 1.0 VDD-1.0
mV dB dB dB MHz V pF k V CL = 20p CL = 20p RL 100 k to VSS PM>40 VO = 4Vpp RL = 50k 1 kHz
Figures are for design aid only: not guaranteed and not subject to production testing. Characteristics are over recommended operating conditions unless otherwise stated.
MT8888C AC Electrical Characteristics
- Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 R X Valid input signal levels (each tone of composite signal)
Sym
Min -29 27.5
Typ
Max +1 869
Units dBm mVRMS
Notes* 1,2,3,5,6 1,2,3,5,6
Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 15.
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Zarlink Semiconductor Inc.
MT8888C
AC Electrical Characteristics
Data Sheet
- Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz Characteristics 1 2 3 4 5 6 7 R X Positive twist accept Negative twist accept Freq. deviation accept Freq. deviation reject Third tone tolerance Noise tolerance Dial tone tolerance 1.5% 2Hz 3.5% -16 -12 22 dB dB dB Sym Min Typ Max 8 8 Units dB dB Notes* 2,3,6,9 2,3,6,9 2,3,5 2,3,5 2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *See "Notes" following AC Electrical Characteristics Tables.
AC Electrical Characteristics- Call Progress
- Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 Accept Bandwidth Lower freq. (REJECT) Upper freq. (REJECT) Call progress tone detect level (total power)
Sym fA fLR fHR
Min 310
Typ
Max 500
Units Hz Hz Hz dBm
Conditions @ -25 dBm, Note 9 @ -25 dBm @ -25 dBm
290 540 -30
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics - DTMF Reception
- Typical DTMF tone accept and reject requirements. Actual values are user selectable as per Figures 5, 6 and 7.
Characteristics 1 2 3 4 Minimum tone accept duration Maximum tone reject duration Minimum interdigit pause duration Maximum tone drop-out duration
Sym tREC tREC tID tDO
Min
Typ 40 20 40 20
Max
Units ms ms ms ms
Conditions
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
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Zarlink Semiconductor Inc.
MT8888C
AC Electrical Characteristics
Data Sheet
- Voltages are with respect to ground (VSS), unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
X T A L T O N E O U T T O N E I N
Sym tDP tDA tPStb3 tPStRX tBST tPS tBSTE tPSE VHOUT VLOUT dBP THD fD RLT fC tCLRF DCCL CLO
Min 3 0.5
Typ 11 4 13 8
Max 14 8.5
Units ms ms s s
Conditions Note 11 Note 11 See Figure 7 See Figure 7 DTMF mode DTMF mode Call Progress mode Call Progress mode RL=10k RL=10k RL=10k 25 kHz Bandwidth RL=10k fC=3.579545 MHz
Tone present detect time Tone absent detect time Delay St to b3 Delay St to RX0-RX3 Tone burst duration Tone pause duration Tone burst duration (extended) Tone pause duration (extended) High group output level Low group output level Pre-emphasis Output distortion (Single Tone) Frequency deviation Output load resistance Crystal/clock frequency Clock input rise and fall time Clock input duty cycle Capacitive load (OSC2)
50 50 100 100 -6.1 -8.1 0 2 -35 0.7 10
52 52 104 104 -2.1 -4.1 3
ms ms ms ms dBm dBm dB dB
1.5 50 110
% k MHz ns % pF
3.5759 3.5795 3.5831 40 50 60 30
Ext. clock Ext. clock
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics- MPU Interface
- Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 RD/WR clock frequency RD/WR cycle period RD/WR rise and fall time Address setup time Address hold time Data hold time (read) RD to valid data delay (read) RD, WR pulse width low RD, WR pulse width high Data setup time (write)
Sym fCYC tCYC tR, tF tAS tAH tDHR tDDR tPWL tPWH tDSW
Min
Typ 4.0 250
Max
Units MHz ns
Conditions Figure 18 Figure 18 Figure 18 Figures 19 & 20 Figures 19 & 20 Figures 19 & 20 Figures 19 & 20 Figures 18, 19 & 20 Figures 18, 19 & 20 Figures 19 & 20
20 23 26 22 100 150 100 45
ns ns ns ns ns ns ns ns
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Zarlink Semiconductor Inc.
MT8888C
AC Electrical Characteristics- MPU Interface (continued)
- Voltages are with respect to ground (VSS), unless otherwise stated.
Data Sheet
Characteristics 11 12 Data hold time (write) Input Capacitance (data bus)
Sym tDHW CIN
Min 10
Typ
Max
Units ns
Conditions Figures 19 & 20
5
pF
13 Output Capacitance (IRQ/CP) COUT 5 pF Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. Digit sequence consists of all 16 DTMF tones. Tone duration=40 ms. Tone pause=40 ms. Nominal DTMF frequencies are used. Both tones in the composite signal have an equal amplitude. The tone pair is deviated by 1.5%2 Hz. Bandwidth limited (3 kHz) Gaussian noise. The precise dial tone frequencies are 350 and 440 Hz (2%). Guaranteed by design and characterization. Not subject to production testing. Referenced to the lowest amplitude tone in the DTMF signal. For guard time calculation purposes.
tCYC tR RD/WR tPWH tF tPWL
Figure 18 - RD/WR Clock Pulse
tPWL RD tPWH tAS CS, RS0 tDDR tDHR tAH
DATA BUS
Figure 19 - 8031/8051/8085 Read Timing Diagram
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Zarlink Semiconductor Inc.
MT8888C
tPWL WR tAS CS, RS0 tDSW tDHW tPWH tAH
Data Sheet
DATA BUS
Figure 20 - 8031/8051/8085 Write Timing Diagram
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Zarlink Semiconductor Inc.
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